| Category | Assignment | Subject | Education |
|---|---|---|---|
| University | Coventry University (CU) | Module Title | PSB5037EE Manufacture of Electronic Systems for Regulatory Compliance |
| Assessment Type | CW1 |
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Module Code and Title PSB5037EE Manufacture of Electronic Systems for Regulatory Compliance |
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Assignment No. / Title CW 1 – Manufacturing Package for Wireless Bluetooth Intelligent Security Box/Safe |
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Submit CW 1 Report Date: < Mid-term> |
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Estimated Time (hrs.) |
Assignment type: Team of 2 |
% of Module Mark CW Part 1 = 50 |
Hand out date: CW Part 1 <Week 1 > |
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No late work accepted. Extensions allowed only in extenuating circumstances. It is important that the work submitted is an individual effort. The penalties for plagiarism are severe. |
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You are the Chief Regulatory and Manufacturing Engineering team of Charlton Co & Ltd, and you are tasked to work on a project titled “Wireless Bluetooth Intelligent Security Box/Safe” to bring the product through regulatory certification and manufacturing readiness for the USA market.
You are to plan, prepare, document for:
CW 1: Manufacturing to bring the PCBA from DFx design consideration, through pilot run, mass production ready for product launch of a regulatory certified box/safe.
Prepare a proposal with a detailed report and explain the strategy taken, and the various documentation package for DFx, quality and reliability testing, functional test and its jig, preregulatory certification testing, and manufacturing package.
The following must be included.
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Buy Non Plagiarized Assignment| CW1 PSB5037EE (Mfg) MS | Marks (Max 100 marks) |
Comment |
| Grand Total | 100 | |
| 1. Technical File | 20 | |
| Ans: | ||
| – List the component failure mechanism, reason, mode and type of failures per prototype build required (LO1) | 3 | |
| – Product Design Technical specification | 2 | |
| – Hardware Architecture Block Diagram and Circuit Principle of Operation | 2 | |
| – Schematic diagram | 3 | |
| – PCB layout | 3 | |
| – Bill-of-Material with UL Rating, Tape & Reel information | 2 | |
| – Technical Design Risk Assessment | 3 | |
| – Thermal Profile Risk Assessment | 2 | |
| 2. The following DFx must be included: | 44 | |
| a. DFQ Design for Quality and Reliability. | 10 | |
| Ans: | ||
| Design for Quality: (LO2A) | ||
| – Design of a safe/box, and it’s components with sufficient voltage, current, power rating considerations. | 1 | |
| – Design of a safe/box, and it’s components with sufficient temperature considerations | 1 | |
| – Parts selection with UL rating, ROHS compliant requirements. | 2 | |
| – Thermal profiling of board, component for overheat. | 2 | |
| – Emission test (Conducted and Radiated) | 2 | |
| – Immunity test (Conducted and Radiated), including ESD | 2 | |
| Ans: | ||
| Design for Reliability: (LO2A) | 10 | |
| – Thermal cycling test | 2 | |
| – Drop test | 2 | |
| – Vibration test | 2 | |
| – IPx dust test | 2 | |
| – 100K Button push test | 1 | |
| – Mechanical force open test | 1 | |
| b. DFT Design for Testability. (LO2D) | 4 | |
| – Test points for probe access | 2 | |
| – Clearance between components. | 2 | |
| c. DFM Design for Manufacturability. (LO2B) | 8 | |
| – PCB Manufacturer’s requirements | 2 | |
| o Current handling capability | – | |
| ^ PCB trace thickness | 1 | |
| ^ PCB trace-to-trace clearance | 1 | |
| ^ PCB trace-to-pad clearance | 1 | |
| o Components to edge of board clearance | 1 | |
| o Component to component clearance for pick and place machine and desoldering | 1 | |
| o Panel size and orientation | 1 | |
| d. DFR : Design for Regulatory Certification (LO2C) | 12 | |
| – UL 60950-1 or UL 62368-1 (newer) Regulatory standard considerations | 4 | |
| – FCC Part 15A Regulatory Standard for intentional radiators considerations | 2 | |
| – FCC Part 15B for electromagnetic compatibility (EMC) of electronic devices | 2 | |
| – Design for reduced emission on trace loop area considerations | 2 | |
| – PCB ground plane and Vcc plane considerations | 2 | |
| 3. PCB Fabrication Package: (LO3) | 2 | |
| – PCB Gerber files for PCB fabrication | 1 | |
| – PCB Penalization document | 1 | |
| 4. Factory Documentation package for manufacturing (LO3) | 12 | |
| – Stencil fabrication for solder paste | 1 | |
| – Component assembly procedure | 2 | |
| – Functional Test procedure | 2 | |
| – Electronic board diagnostic procedure | 2 | |
| – PCBA Assembly Instructions | 2 | |
| – Process flow chart | 2 | |
| 5. Failure Analysis and Failure Modes Identification (LO1) | 22 | |
| o List potential failure modes for each component and functional block. | 4 | |
| o List common failure modes such as open circuits, short circuits, and component degradation. | 4 | |
| o Evaluate the criticality and impact of identified failure modes. | 2 | |
| o Prioritize potential failures based on safety, functionality, and user impact. | 2 | |
| o Propose corrective actions to address identified failure modes. | 2 | |
| o Consider design improvements, component replacements, or changes to manufacturing processes. | 2 | |
| o Verify that the corrective actions effectively mitigate the identified failure modes. | 2 | |
| o Validate the changes through testing and simulation. | 2 |
Only one team report should be submitted by one team member and should include team members names. This should be a PDF file. (Please make sure that the conversion from Word to PDF follows the correct formatting).
The assignment report’s file name should begin with the team’s name and the up-loader’s surname. The other team members should upload a cover sheet with the filename: coversheet followed by the team’s name. The cover sheet template is provided on Blackboard.
Note: it is very important that the work submitted is an individual effort.
Keep a safe copy of all coursework submitted for reference.
No copying is allowed.
The use of AI Tools such as ChatGPT is not allowed.
Student found to plagiarize may be referred to the school for action and zero marks will be awarded for any number of students involved.
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