ICT114: Computer Architecture Tutor-Marked Assignment January 2025 Semester Presentation | SUSS

Published: 01 Apr, 2025
Category Assignment Subject Computer Science
University Singapore University of Social Sciences (SUSS) Module Title ICT114: Computer Architecture ICT114: the instruction format shown in Figure Q2(i)

Question 1

A digital system uses 8-bit for integer representation and 32-bit for floating point number representation. Explain and analyse the various number representations and answer the following questions.

A. If the code word 1111 1010 is to be interpreted as a fixed-point fraction with four bits before and four bits after the binary point.

  1. Give the binary representation of this number.
  2. Compute the decimal value of this number if both the integral and fractional
    parts are unsigned representations.

B. Express AB16 and FF16 in 8-bit binary representation. Then find the result of AB16 XOR FF16 in binary and express the answer in hexadecimal. How is the result of this
expression related to AB16?

  1. Express 38 and -70 in 8-bit 2’s complement signed integer representation.
  2. Find the result of 38 – 70 by performing the computation in 2’s complement arithmetic. Assume 2’s complement arithmetic is performed by adding 38 + (-70). Verify that the result of the 2’s complement arithmetic is equivalent to the
    decimal result.

C. The hexadecimal number C260 0000 represents a 32-bit floating point number. Its representation is given in Figure Q1(d). What is the decimal value? Show your working.

ICT114: Computer Architecture

  1. One mark will be deducted from each sub-section if subscripts are not shown for hexadecimal and binary numbers, or their number bases are not indicated.
  2. When an equal sign is used, the left side must be equal to the right side. A penalty will be imposed for the misuse of the equal sign.

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Question 2

Figure Q2 shows the characteristics of a hypothetical machine, relevant portions of memory, processor registers and some I/O devices. For the instruction format shown in Figure Q2(i), if it is an I/O instruction, bits 4 to 15 identify a particular I/O device. If it is not an I/O instruction,it is a memory address.

ICT114: Computer Architecture

  1. How many memory locations can this processor address?
  2. This hypothetical machine is to execute the following program:
  1. Load AC from device 3.
  2. Add contents of memory location 991.
  3. Store AC to memory location 992.

There are three fetch and three execute cycles. The process can be divided into six steps or cycles. For each step or cycle, demonstrate what happens and list the contents of the following registers:

  1. PC at the start of each cycle,
  2. AC at the end of each cycle and
  3. IR at the end of each cycle.

Assume the initial values are as given in Figure Q2(v). Summarise your answer using the format shown in Table Q2.


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