J/651/0739 Unit 4020 Digital Principles Assessment Brief – Explain Combinational Logic Circuits

ASSESSMENT BRIEF

Unit Title: Digital Principles
Unit Number: 4020
Unit Code: J/651/0739

Outcome LO1 Explain combinational logic circuits

Assessment No.: 1 of 4

Assessment Title: Explain combinational logic circuits

ASSESSMENT CRITERIA

Activity

Holistically, you are required to design combinational logic circuits by making best use of Truth, Tables, Boolean Alegeba and Karnaugh Map.

Following the steps below should help with this.

1. Explain what is meant by a combinational logic circuit?
2. You have been assigned to a ‘P’ column in Table 1 below. Write down the Boolean equation for the P that was assigned to you.
3. Use a K-map to see if the Boolean output from the P value can be minimised. Here, you should group the 1’s only for a sum of products result. Show all evidence of K map use. You may use proofing tools provided all work has been completed from first principles. (~200 words)
4. Your line manager has asked you to analyse a 3-input majority vote taker (the same circuit could be used in a Car for error checking). This will be for three ‘participants’ and such that it will illuminate an LED if two or more vote yes (a logic ‘1’). Otherwise, if there is no majority vote, the LED should remain off. You are expected to write down the truth table and from that write down the Boolean output.
5. By using a Karnaugh map, optimise (minimise) your initial design.
6. Use De-Morgan’s Theorem to design a NAND only solution. Show all working.
7. Verify that this design works in Multisim. Include evidence.
8. List at least one advantage of using De-Morgan’s Theorem.

(~300 words)