ELEC 2141 Digital Circuit Design Assignment 2 Term 01 2025 | UNSW

ELEC 2141 Digital Circuit Design Assignment 2 

Your assignment solutions are to be submitted in PDF format on Moodle. Combine all scanned copies of your handwritten work and electronic documents into one PDF file for the submission. 

In your submission file, include a scanned copy of a completed and signed assignment submission form as the front page. 

Your design should aim at achieving an optimised implementation. Your report should include your design procedure, choice of technology implementation, and simulation results. The gate input cost must also be calculated. Use Vivado to simulate and verify your design.

Attach all design and simulation materials such as schematic diagram (or HDL), simulation outputs and testing fixtures. 

Any output of generative AI software used within your assignment must be attributed with full referencing. If the outputs of generative AI such as ChatGPT form part of your submission and are not appropriately attributed, it will be regarded as serious academic misconduct and subject to the standard penalties, which may include 00FL, suspension and exclusion. 

*To cite: OpenAI (Year Accessed). ChatGPT. OpenAI. *Please note that the outputs from these tools are not always accurate, appropriate, or properly referenced. You should ensure that you have moderated and critically evaluated the outputs from generative AI tools such as ChatGPT before submission.

ARC UNSW is back again. Their sponsor was so impressed with your efforts in assignment 1 that they have a second task for you! 

ARC has decided to make the escape room more difficult. To achieve this, teams will be given a limited amount of time to complete the escape room; each challenge will have an equal amount of time. They want you to design a finite state machine (FSM) that controls the amount of time teams have available to complete the three challenges in the escape room presented in Assignment 1. The FSM controlling time available to the teams is reset when the start button is pressed (START = 1). The FSM will stay on until the end of the sequence. It sequences through an initial reading time, challenge 1, challenge 2 and challenge 3 and then returns to the start. The same amount of time is allocated to the initial reading time and each of the three challenges. 

An external timer tracks the duration allotted for each challenge. It begins ticking as soon as the start button is pressed. The timer generates an output (TIME = 1) at the end of its duration, which is fed as an input to the FSM. It then resets itself and starts again. COMP from challenge 1, OUTS from challenge 2 and CODE from challenge 3 are additional inputs to the FSM used to prevent teams from working on multiple challenges during the same period. If, while TIME = 0, COMP from challenge 1 has a non-zero value (i.e. COMP ≠ 00) and either OUTS from challenge 2 has a non-zero value (i.e. OUTS ≠ 0000) or CODE from challenge 3 has a non-zero value (i.e. CODE ≠ 0000), the FSM will stay at challenge 1. Similarly, while TIME = 0, if OUTS from challenge 2 has a non-zero value (i.e. OUTS ≠ 0000), COMP from challenge 1 is zero (i.e. COMP = 00) and CODE from challenge 3 has a non-zero value (i.e. CODE ≠ 0000), the FSM will stay at challenge 2. When the time for all three challenges is complete, the FSM will provide an output OVER = 1 and the timer reset for the next team. 

For your assignment, you need to 

1. Identify the system inputs and outputs. 
2. Draw a state diagram for the FSM. 
3. Determine if the number of states can be reduced and assign them with binary codes. 
4. Design and implement the FSM using D, T and JK flip-flops. 
5. Write Verilog HDL models for: 
a. The FSM based on the state diagram in (2) (behavioural modelling) 
b. The JK flip-flop sequential circuit that you implement in (4) (structural or dataflow modelling) 
6. Verify the HDL models in (5)